MC68HC08AZ60A Datasheet, PDF (111/480 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Instruction Set Summary
Table 7-1. Instruction Set Summary (Continued)
Source
Form
Operation
DAA
Decimal Adjust A
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ
opr,X,rel
DBNZ X,rel
DBNZ
opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement and Branch if Not
Zero
Decrement
DIV
Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Increment
Jump
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
Description
Effect on
CCR
VHI NZ C
(A)₁₀
U – – ↕ ↕ ↕ INH
A ← (A) – 1 or M ← (M) – 1 or X ← (X) –
1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
DIR
INH
– – – – – – INH
IX1
IX
SP1
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
DIR
INH
↕
–
–
↕
↕
–
INH
IX1
IX
SP1
– – – – ↕ ↕ INH
A ← (A ⊕ M)
IMM
DIR
EXT
0
–
–
↕
↕
–
IX2
IX1
IX
SP1
SP2
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
DIR
INH
↕
–
–
↕
↕
–
INH
IX1
IX
SP1
DIR
EXT
– – – – – – IX2
IX1
IX
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
72
2
3B dd 5
4B rr 3
5B rr 3
6B rr 5
7B ff rr 4
9E rr 6
6B ff rr
3A
4A
dd
5A
6A
7A
ff
9E
6A
ff
4
1
1
4
3
5
52
7
A8
B8
C8
D8
E8
F8
9E
ii
dd
hh
ll
ee
ff
ff
2
3
4
4
3
2
E8
9E
D8
ff
ee
ff
4
5
3C
4C
dd
5C
6C
7C
ff
9E
6C
ff
4
1
1
4
3
5
dd
BC hh 2
CC ll
3
DC ee 4
EC ff
3
FC ff
2
dd
BD hh 4
CD ll
5
DD ee 6
ED ff
5
FD ff
4
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Central Processor Unit (CPU)
Advance Information
111