MC68HC08AZ60A Datasheet, PDF (294/480 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module B (TIMB)
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/ATD12/TBCLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIMB clock input. When the
PTD4/ATD12/TBCLK pin is the TIMB clock input, it is an input regardless
of the state of the DDRD4 bit in data direction register D.
18.8.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTF4/TBCH0 and PTF5/TBCH1
can be configured as buffered output compare or buffered PWM pins.
18.9 I/O Registers
These I/O registers control and monitor TIMB operation:
• TIMB status and control register (TBSC)
• TIMB control registers (TBCNTH–TBCNTL)
• TIMB counter modulo registers (TBMODH–TBMODL)
• TIMB channel status and control registers (TBSC0 and TBSC1)
• TIMB channel registers (TBCH0H–TBCH0L, TBCH1H–TBCH1L)
Advance Information
294
Timer Interface Module B (TIMB)
MC68HC08AZ60A — Rev 0.0
MOTOROLA