MC68HC08AZ60A Datasheet, PDF (118/480 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
8.9 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.9.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . 134
8.9.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . 136
8.9.3 SIM Break Flag Control Register (SBFCR). . . . . . . . . . . 137
8.2 Introduction
This section describes the system integration module, which supports up
to 24 external and/or internal interrupts. Together with the CPU, the SIM
controls all MCU activities. A block diagram of the SIM is shown in
Figure 8-1. Table 8-1 is a summary of the SIM I/O registers. The SIM is
a system state controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– STOP/WAIT/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Advance Information
118
System Integration Module (SIM)
MC68HC08AZ60A — Rev 0.0
MOTOROLA