MC68HC08AZ60A Datasheet, PDF (193/480 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP)
COP Control Register (COPCTL)
13.5 COP Control Register (COPCTL)
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Bit 7
6
5
4
3
2
1
Bit 0
COPCTL ^Read:
$FFFF _Write:
Low byte of reset vector
Clear COP counter
Reset:
Unaffected by reset
Figure 13-2. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when V_HI is present on the IRQ pin
or on the RST pin.
13.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
13.8.1 WAIT Mode
The COP continues to operate during WAIT mode. To prevent a COP
reset during WAIT mode, the COP counter should be cleared
periodically in a CPU interrupt routine.
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Computer Operating Properly (COP)
Advance Information
193