MC68HC08AZ60A Datasheet, PDF (422/480 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module A (TIMA)
23.9.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes
of the value in the TIMA counter. Reading the high byte (TACNTH)
latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL
is read. Reset clears the TIMA counter registers. Setting the TIMA reset
bit (TRST) also clears the TIMA counter registers.
NOTE:
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL
by reading TACNTL before exiting the break interrupt. Otherwise,
TACNTL retains the value latched during the break.
Register Name and Address TACNTH — $0022
Bit 7
6
5
4
3
2
1
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
Write: R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
Bit 0
BIT 8
R
0
Register Name and Address TACNTL — $0023
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 23-5. TIMA Counter Registers (TACNTH and TACNTL)
Advance Information
422
Timer Interface Module A (TIMA)
MC68HC08AZ60A — Rev 0.0
MOTOROLA