MC68HC08AZ60A Datasheet, PDF (206/480 Pages) Motorola, Inc – Microcontrollers

External Interrupt Module (IRQ)
15.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. See SIM Break Flag Control Register
(SBFCR).
To allow software to clear the IRQ latch during a break interrupt, write a
logic ’1’ to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic ‘0’ to the BCFE
bit. With BCFE at logic ‘0’ (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
15.6 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR performs the following functions:
• Indicates the state of the IRQ interrupt flag
• Clears the IRQ interrupt latch
• Masks IRQ interrupt requests
• Controls triggering sensitivity of the IRQ interrupt pin
Address: $001A
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
IRQF
0
IMASK MODE
Write: R
R
R
R
R
ACK
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 15-3. IRQ Status and Control Register (ISCR)
Advance Information
206
External Interrupt Module (IRQ)
MC68HC08AZ60A — Rev 0.0
MOTOROLA