MC68HC08AZ60A Datasheet, PDF (296/480 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module B (TIMB)
TSTOP — TIMB Stop Bit
This read/write bit stops the TIMB counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB
counter until software clears the TSTOP bit.
1 = TIMB counter stopped
0 = TIMB counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIMB is
required to exit wait mode. Also, when the TSTOP bit is set and the timer
is configured for input capture operation, input captures are inhibited
until TSTOP is cleared.
TRST — TIMB Reset Bit
Setting this write-only bit resets the TIMB counter and the TIMB
prescaler. Setting TRST has no effect on any other registers. Counting
resumes from $0000. TRST is cleared automatically after the TIMB
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIMB counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB
counter at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/ATD12/TBCLK pin or
one of the seven prescaler outputs as the input to the TIMB counter
as Table 18-1 shows. Reset clears the PS[2:0] bits.
PS[2:0]
000
001
010
011
100
101
110
111
Table 18-1. Prescaler Selection
TIMB Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD4/ATD12/TBCLK
Advance Information
296
Timer Interface Module B (TIMB)
MC68HC08AZ60A — Rev 0.0
MOTOROLA