MC68HC08AZ60A Datasheet, PDF (160/480 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
9.8.2 Stop Mode
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If CGMOUT is being driven by CGMVCLK and a STOP instruction is
executed; the PLL will clear the BCS bit in the PLL control register,
causing CGMOUT to be driven by CGMXCLK. When the MCU recovers
from STOP, the crystal clock divided by two drives CGMOUT and BCS
remains clear.
9.9 CGM During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Break Module on page
171).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
9.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
9.10.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
Advance Information
160
Clock Generator Module (CGM)
MC68HC08AZ60A — Rev 0.0
MOTOROLA