MC68HC08AS32 Datasheet, PDF (93/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

5.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating
modes:
• Acquisition mode — In acquisition mode, the filter can make large (see
17.10 CGM Acquisition/Lock Time Information) frequency corrections to
the VCO. This mode is used at PLL startup or when the PLL has suffered a
severe noise hit and the VCO frequency is far off the desired frequency.
When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. (See 5.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small (see 17.10
CGM Acquisition/Lock Time Information) corrections to the frequency of
the VCO. PLL jitter is much lower in tracking mode, but the response to
noise is also slower. The PLL enters tracking mode when the VCO
frequency is nearly correct, such as when the PLL is selected as the base
clock source. (See 5.3.3 Base Clock Selector Circuit.) The PLL is
automatically in tracking mode when not in acquisition mode or when the
ACQ bit is set.
5.3.2.3 Automatic and Manual PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually
or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically
switches between acquisition and tracking modes. Automatic bandwidth control
mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as
the source for the base clock, CGMOUT. (See 5.5.2 PLL Bandwidth Control
Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In
either case, when the LOCK bit is set, the VCO clock is safe to use as the source
for the base clock. (See 5.3.3 Base Clock Selector Circuit.) If the VCO is selected
as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the
application. (See 5.6 Interrupts for information and precautions on using
interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control
mode:
• The ACQ bit (see 5.5.2 PLL Bandwidth Control Register) is a read-only
indicator of the mode of the filter. (See 5.3.2.2 Acquisition and Tracking
Modes.)
• The ACQ bit is set when the VCO frequency is within a certain tolerance,
∆_TRK, and is cleared when the VCO frequency is out of a certain tolerance,
∆_UNT. (See 5.9 Acquisition/Lock Time Specifications for more
information.)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
93