MC68HC08AS32 Datasheet, PDF (78/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Table 4-2. BDLC Transceiver Delay (Continued)
BARD Offset Bits B0[3:0]
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Corresponding Expected
Transceiver’s Delays (µs)
14
15
16
17
18
19
20
21
22
23
24
4.6.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
IMSG
CLKS
R1
R0
0
R
0
R
IE
WCM
Reset:
1
1
1
0
0
0
0
0
R = Reserved
Figure 4-18. BDLC Control Register 1 (BCR1)
IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF) is
detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be masked
and the status bits will be held in their reset state. If this bit is set while
the BDLC is receiving a message, the rest of the incoming message will
be ignored.
0 = Enable receiver. This bit is cleared automatically by the reception of an
SOF symbol or a BREAK symbol. It will then generate interrupt requests
and will allow changes of the status register to occur. However, these
interrupts may still be masked by the interrupt enable (IE) bit.
Data Sheet
78
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor