MC68HC08AS32 Datasheet, PDF (211/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

BUS
CLOCK
MOSI
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
WRITE
TO SPDR
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
BUS
CLOCK
WRITE
TO SPDR
EARLIEST LATEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 14-8. Transmission Start Delay (Master)
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE in SPSCR) is also set. MODF and OVRF can generate a receiver/error
CPU interrupt request. (See Figure 14-11.) It is not possible to enable only MODF
or OVRF to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out of wait,
having an overflow condition without overflow interrupts enabled causes the MCU
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
211