MC68HC08AS32 Datasheet, PDF (190/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 13-8. POR Recovery
13.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal
instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a
reset.
NOTE: A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode (stop
instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the MOR register is logic 0, the SIM treats the STOP
instruction as an illegal opcode and causes an illegal opcode reset.
13.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset.
The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit
in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset.
13.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when the V_DD
voltage falls to the V_LVIF voltage. The LVI bit in the SIM reset status register
(SRSR) is set and a chip reset is asserted if the LVIPWR and LVIRST bits in the
CONFIG register are at logic 1. The RST pin will be held low until the SIM counts
4096 CGMXCLK cycles after V_DD rises above V_LVIR. Another 64 CGMXCLK cycles
later, the CPU is released from reset to allow the reset vector sequence to occur.
(See Section 9. Low-Voltage Inhibit (LVI).)
Data Sheet
190
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor