MC68HC08AS32 Datasheet, PDF (257/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

16.3.1.1 Entering Monitor Mode
Table 16-1 shows the pin conditions for entering monitor mode.
NOTE:
Table 16-1. Mode Selection
IRQ
Pin
PTCO
PIN
PTC1
PIN
PTA0
PIN
PTC3
PIN
MODE
CGMOUT
Bus
Frequency
V_DD +
V_HI(1)
1
0
1
1 Monitor ^{C-----G----M-----X-----C----L---K---} or ^{C-----G----M-----V-----C----L---K--- C-----G----M------O----U----T---}
2
2
2
V_DD +
V_HI(1)
1
0
1
0 Monitor
CGMXCLK
C-----G----M------O----U----T---
2
1. For V_HI, see 17.4 5.0-Volt DC Electrical Characteristics and 17.1 Maximum Ratings
Enter monitor mode by either:
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin
The MCU sends a break signal (10 consecutive logic 0s) to the host computer,
indicating that it is ready to receive a command. The break signal also provides a
timing reference to allow the host to determine the necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The
alternate vectors are in the $FE page instead of the $FF page and allow code
execution from the internal monitor firmware instead of user code. The COP
module is disabled in monitor mode as long as V_DD + V_HI (see 17.4 5.0-Volt DC
Electrical Characteristics) is applied to either the IRQ pin or the V_DD pin. (See
Section 13. System Integration Module (SIM) for more information on modes of
operation.)
Holding the PTC3 pin low when entering monitor mode causes a bypass of a
divide-by-two stage at the oscillator. The CGMOUT frequency is equal to the
CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks.
In this case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Table 16-2 is a summary of the differences between user mode and monitor mode.
Table 16-2. Mode Differences
Modes
User
Monitor
COP
Enabled
Disabled⁽¹⁾
Reset
Vector High
$FFFE
$FEFE
Reset
Vector Low
$FFFF
$FEFF
Functions
Break
Vector High
$FFFC
$FEFC
Break
Vector Low
$FFFD
$FEFD
SWI
Vector High
$FFFC
$FEFC
SWI
Vector Low
$FFFD
$FEFD
1. If the high voltage (V_DD + V_HI) is removed from the IRQ/V_PP pin while in monitor mode, the SIM asserts its COP enable output.
The COP is a mask option enabled or disabled by the COPD bit in the configuration register. (See 17.4 5.0-Volt DC Electrical
Characteristics.)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
257