MC68HC08AS32 Datasheet, PDF (47/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
READ PTB/PTD
DDRBx/DDRDx
PTBx/PTDx
ADC DATA REGISTER
DISABLE
PTBx/PTDx
ADC CHANNEL x
DISABLE
CONVERSION
INTERRUPT ^COMPLETE
LOGIC
AIEN
COCO
CGMXCLK
BUS CLOCK
ADC
ADC VOLTAGE IN
ADCVIN
CHANNEL ^ADCH[4:0]
SELECT
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0] ADICLK
Figure 3-2. ADC Block Diagram
3.3.1 ADC Port I/O Pins
PTD6/ATD14/TCLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are general-
purpose I/O pins that are shared with the ADC channels.
The channel select bits (ADC status control register, $0038), define which ADC
channel/port pin will be used as the input signal. The ADC overrides the port I/O
logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins
are controlled by the port I/O logic and can be used as general-purpose I/O. Writes
to the port register or DDR will not have any affect on the port pin that is selected
by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port
data latch is read.
NOTE: Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin as the
clock input for the TIM.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
47