MC68HC08AS32 Datasheet, PDF (62/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

4.4.1.2 Performance
The performance of the digital filter is best described in the time domain rather than
the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay before that
transition appears at the filtered Rx data output signal. This delay will be between
15 and 16 clock periods, depending on where the transition occurs with respect to
the sampling points. This filter delay must be taken into account when performing
message arbitration.
For example, if the frequency of the MUX interface clock (f_BDLC) is 1.0486 MHz,
then the period (t_BDLC) is 954 ns and the maximum filter delay in the absence of
noise will be 15.259 µs.
The effect of random noise on the BDRxD signal depends on the characteristics of
the noise itself. Narrow noise pulses on the BDRxD signal will be ignored
completely if they are shorter than the filter delay. This provides a degree of low
pass filtering.
If noise occurs during a symbol transition, the detection of that transition can be
delayed by an amount equal to the length of the noise burst. This is just a reflection
of the uncertainty of where the transition is truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest
allowable symbol length, will be detected by the next stage of the BDLC’s receiver
as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length will be
detected normally as an invalid symbol or as invalid data when the frame’s CRC is
checked.
4.4.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using the format shown
in Figure 4-7.
J1850 states that each message has a maximum length of 101 PWM bit times or
12 VPW bytes, excluding SOF, EOD, NB, and EOF, with each byte transmitted
MSB first.
All VPW symbol lengths in the following descriptions are typical values at a
10.4 kbps bit rate.
IDLE SOF
DATA
PRIORITY
(DATA0)
MESSAGE ID
(DATA1)
DATA_N
E
OPTIONAL
CRC
ON
DB
IFR
I
EOF
F
S
IDLE
Figure 4-7. J1850 Bus Message Format (VPW)
Data Sheet
62
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor