MC68HC08AS32 Datasheet, PDF (65/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

IDLE — Idle Bus
An idle condition exists on the bus during any passive period after expiration of
the IFS period (for instance, ≥ 300 µs). Any node sensing an idle bus condition
can begin transmission immediately.
4.4.3 J1850 VPW Symbols
Huntsinger’s variable pulse width modulation (VPW) is an encoding technique in
which each bit is defined by the time between successive transitions and by the
level of the bus between transitions (for instance, active or passive). Active and
passive bits are used alternately. This encoding technique is used to reduce the
number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active
or passive level and one of two lengths, either 64 µs or 128 µs (t_NOM at 10.4 kbps
baud rate), depending upon the encoding of the previous bit. The start-of-frame
(SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame separation (IFS)
symbols always will be encoded at an assigned level and length. See Figure 4-8.
ACTIVE
PASSIVE
128 µs
OR
64 µs
(A) LOGIC 0
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
128 µs
OR
(B) LOGIC 1
64 µs
≥ 240 µs
200 µs
200 µs
(C) BREAK
280 µs
(D) START OF FRAME
300 µs
20 µs
(E) END OF DATA
IDLE > 300 µs
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 4-8. J1850 VPW Symbols with Nominal Symbol Times
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
65