MC68HC08AS32 Datasheet, PDF (187/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 13-4. CGM Clock Signals
13.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not
become active until after the stop delay timeout. This timeout is selectable as
4096 or 32 CGMXCLK cycles. (See 13.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. However, some modules can be
programmed to be active in wait mode. Refer to the wait mode subsection of each
module to see if the module is active or inactive in wait mode.
13.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
Each of these resets produces the vector $FFFE–FFFF ($FEFE–FEFF in monitor
mode) and asserts the internal reset signal (IRST). IRST causes all registers to be
returned to their default values and all modules to be returned to their reset states.
An internal reset clears the SIM counter (see 13.4 SIM Counter), but an external
reset does not. Each of the resets sets a corresponding bit in the SIM reset status
register (SRSR). (See 13.7 SIM Registers.)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
187