MC68HC08AS32 Datasheet, PDF (273/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

17.15 BDLC Receiver VPW Symbol Timings
Characteristic^{(1), (2), (3)}
Number Symbol
Min
Typ
Max
Unit
Passive logic 0
10
t_TRVP1
34
64
96
µs
Passive logic 1
11
t_TRVP2
96
128
163
µs
Active logic 0
12
t_TRVA1
96
128
163
µs
Active logic 1
13
t_TRVA2
34
64
96
µs
Start-of-frame (SOF)
14
t_TRVA3
163
200
239
µs
End-of-data (EOD)
15
t_TRVP3
163
200
239
µs
End-of-frame (EOF)
16
t_TRV4
239
280
320
µs
Break
18
t_TRV6
280
—
—
µs
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 t_BDLC µs due to sampling considerations.
3. See Figure 17-3.
14
10
12
SOF
13
11
0
0
15
1
1
0
EOD
16
EOF
18
BRK
Figure 17-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
273