MC68HC08AS32 Datasheet, PDF (71/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

ACTIVE
TRANSMITTER A
PASSIVE
ACTIVE
TRANSMITTER B
PASSIVE
ACTIVE
J1850 BUS
PASSIVE
0
1
1
1
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
0
1
1
0
0
0
1
1
0
0
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
DATA DATA DATA
DATA DATA
SOF
BIT 1 BIT 2
BIT 3
BIT 4
BIT 5
Figure 4-13. J1850 VPW Bitwise Arbitrations
The variable pulse width modulation (VPW) symbols and J1850 bus electrical
characteristics are chosen carefully so that a logic 0 (active or passive type) will
always dominate over a logic 1 (active or passive type) that is simultaneously
transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to be
recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a
recessive bit, the node loses arbitration and immediately stops transmitting. This is
known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value will have
the highest priority and will always win arbitration. For instance, a message with
priority 000 will win arbitration over a message with priority 011.
This method of arbitration will work no matter how many bits of priority encoding
are contained in the message.
During arbitration, or even throughout the transmitting message, when an opposite
bit is detected, transmission is stopped immediately unless it occurs on the 8th bit
of a byte. In this case, the BDLC automatically will append up to two extra logic 1
bits and then stop transmitting. These two extra bits will be arbitrated normally and
thus will not interfere with another message. The second logic 1 bit will not be sent
if the first loses arbitration. If the BDLC has lost arbitration to another valid
message, then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then the two
extra logic 1s will ensure that the current message will be detected and ignored as
a noise-corrupted message.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
71