MC68HC08AS32 Datasheet, PDF (72/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

4.5 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler conforms to SAE
J1850 — Class B Data Communications Network Interface.
NOTE: Freescale assumes that the reader is familiar with the J1850 specification before
this protocol handler description is read.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-14. BDLC Block Diagram
4.5.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx shadow
register, Rx shift register, Tx shift register, and loopback multiplexer as shown in
Figure 4-15.
4.5.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus and
makes them available in parallel form to the Rx shadow register. The Tx shift
register takes data, in parallel form, from the Tx shadow register and presents it
serially to the state machine so that it can be transmitted onto the J1850 bus.
Data Sheet
72
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor