MC68HC08AS32 Datasheet, PDF (198/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

13.7 SIM Registers
The SIM has three memory mapped registers.
13.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an
exit from stop mode or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
R
R
R
R
R
R
SBSW
R
Reset:
0
R
= Reserved
Figure 13-18. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait mode or stop
mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it.
Reset clears SBSW.
1 = Stop mode or wait mode exited by break interrupt
0 = Stop mode or wait mode not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the
return address on the stack by subtracting one from it. The following code is an
example of this. Writing 0 to the SBSW bit
clears it.
;This code works if the H register has been pushed onto the stack in the break service
;routine software. This code should be executed at the end of the break service
;routine software.
HIBYTE EQU
5
LOBYTE EQU
6
;
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN ;See if wait mode or stop mode was exited by
;break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN PULH
;Restore H register.
RTI
Data Sheet
198
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor