MC68HC08AS32 Datasheet, PDF (253/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

16.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC–$FFFD ($FEFC–$FEFD in
monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If
the break address register match occurs on the last cycle of a CPU instruction, the
break interrupt begins immediately.
16.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
16.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_DD + V_HI is present on the RST
pin. For V_HI, see 17.4 5.0-Volt DC Electrical Characteristics.
16.2.2 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
16.2.2.1 Break Status and Control Register
The break status and control register contains break module enable and status
bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
BRKE
BRKA
0
R
0
R
0
R
0
R
0
R
0
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 16-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear
BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
253