MC68HC08AS32 Datasheet, PDF (178/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

12.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal two conditions:
1. Break character detected
2. Incoming data
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
R
R
R
R
R
R
BKF
RPF
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 12-13. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on
the PTE1/RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit
character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate
a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then
reading the SCDR. Once cleared, BKF can become set again only after logic 1s
again appear on the PTE1/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time
period of the start bit search. RPF does not generate an interrupt request. RPF
is reset after the receiver detects false start bits, usually from noise or a baud
rate mismatch or when the receiver detects an idle character. Polling RPF
before disabling the SCI module or entering stop mode can show whether a
reception is in progress.
1 = Reception in progress
0 = No reception in progress
Data Sheet
178
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor