MC68HC08AS32 Datasheet, PDF (100/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK.
PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT
(BCS = 1). (See 5.3.3 Base Clock Selector Circuit.) Reset sets this bit so that
the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT
frequency is one-half the frequency of the selected clock. BCS cannot be set
while the PLLON bit is clear. After toggling BCS, it may take up to three
CGMXCLK cycles and three CGMVCLK cycles to complete the transition from
one source clock to the other. During the transition, CGMOUT is held in stasis.
(See 5.3.3 Base Clock Selector Circuit.) Reset and the STOP instruction clear
the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
PLLON and BCS have built-in protection that prevents the base clock selector
circuit from selecting the VCO clock as the source of the base clock if the PLL is
off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set
when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires
two writes to the PLL control register. (See 5.3.3 Base Clock Selector Circuit.)
PCTL[3:0] — Unimplemented bits
These bits provide no function and always read as logic 1s.
5.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read: _AUTO
LOCK
ACQ
XLD
0
0
0
0
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 5-5. PLL Bandwidth Control Register (PBWC)
Data Sheet
100
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor