MC68HC08AS32 Datasheet, PDF (207/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a
transmission. When CPHA is clear, the falling edge of SS starts a transmission.
(See 14.5 Transmission Formats.)
If the write to the data register is late, the SPI transmits the data already in the shift
register from the previous transmission.
To prevent SPSCK from appearing as a clock edge, SPSCK must be in the proper
idle state before the slave is enabled.
14.5 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially)
and received (shifted in serially). A serial clock line synchronizes shifting and
sampling on the two serial data lines. A slave select line allows individual selection
of a slave SPI device; slave devices that are not selected do not interfere with SPI
bus activities. On a master SPI device, the slave select line can be used optionally
to indicate a multiple-master bus contention.
14.5.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCK) phase and
polarity using two bits in the SPI control register (SPCR). The clock polarity is
specified by the CPOL control bit, which selects an active high or low clock and has
no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two fundamentally
different transmission formats. The clock phase and polarity should be identical for
the master SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE: Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI by clearing
the SPI enable bit (SPE).
14.5.2 Transmission Format When CPHA = 0
Figure 14-5 shows an SPI transmission in which CPHA (SPCR) is logic 0. The
figure should not be used as a replacement for data sheet parametric
information.Two waveforms are shown for SCK: one for CPOL = 0 and another for
CPOL = 1. The diagram may be interpreted as a master or slave timing diagram
since the serial clock (SCK), master in/slave out (MISO), and master out/slave in
(MOSI) pins are directly connected between the master and the slave. The MISO
signal is the output from the slave, and the MOSI signal is the output from the
master. The SS line is the slave select input to the slave. The slave SPI drives its
MISO output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not shown but is
assumed to be inactive. The SS pin of the master must be high or must be
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
207