MC68HC08AS32 Datasheet, PDF (247/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1 and clear output on compare is selected, setting
the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals
to 100%. As Figure 15-9 shows, the CHxMAX bit takes effect in the cycle after
it is set or cleared. The output stays at 100% duty cycle level until the cycle after
CHxMAX is cleared.
The PWM 0% duty cycle is defined as output low all of the time. To generate the
0% duty cycle, select clear output on compare and then clear the TOVx bit
(CHxMAX = 0). The PWM 100% duty cycle is defined as output high all of the time.
To generate the 100% duty cycle, use the CHxMAX bit in the TSCx register.
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
PTEx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 15-9. CHxMAX Latency
15.8.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input
capture function or the output compare value of the output compare function. The
state of the TIM channel registers after reset is unknown.
In input capture mode (MSxB–MSxA = 0–0), reading the high byte of the TIM
channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is
read.
In output compare mode (MSxB–MSxA ≠ 0–0), writing to the high byte of the TIM
channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is
written.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
247