MC68HC08AS32 Datasheet, PDF (66/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Each message will begin with an SOF symbol an active symbol and, therefore,
each data byte (including the CRC byte) will begin with a passive bit, regardless of
whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values at a
10.4 kbps bit rate.
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period 64 µs in
length, or
– A passive-to-active transition followed by an active period 128 µs in
length
See Figure 4-8(a).
Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period 128 µs in
length, or
– A passive-to-active transition followed by an active period 64 µs in
length
See Figure 4-8(b).
Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is only used
in IFR message responses.
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an
active period of at least 240 µs (see Figure 4-8(c)).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active
period 200 µs in length (see Figure 4-8(d)). This allows the data bytes which
follow the SOF symbol to begin with a passive bit, regardless of whether it is a
logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a
passive period 200 µs in length (see Figure 4-8(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a
passive period 280 µs in length (see Figure 4-8(f)). If no IFR byte is transmitted
after an EOD symbol is transmitted, after another 80 µs the EOD becomes an
EOF, indicating completion of the message.
Data Sheet
66
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor