MC68HC08AS32 Datasheet, PDF (89/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Data Sheet — MC68HC08AS32
Section 5. Clock Generator Module (CGM)
5.1 Introduction
This section describes the clock generator module (CGM). The CGM generates the
crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The
CGM also generates the base clock signal, CGMOUT, from which the system
integration module (SIM) derives the system clocks. CGMOUT is based on either
the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK,
divided by two. The PLL is a frequency generator designed for use with 1-MHz to
16-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz bus
frequency without using a 32-MHz crystal.
5.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of the crystal
reference
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter
operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
5.3 Functional Description
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the
constant crystal frequency clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO
frequency clock, CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either
CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as
the base clock, CGMOUT. The SIM derives the system clocks from
CGMOUT.
Figure 5-1 shows the structure of the CGM.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
89