MC68HC08AS32 Datasheet, PDF (48/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

3.3.2 Voltage Conversion
NOTE:
When the input voltage to the ADC equals V_REFH (see 17.6 ADC Characteristics),
the ADC converts the signal to $FF (full scale). If the input voltage equals
V_SSA/V_REFL the ADC converts it to $00. Input voltages between V_REFH and
V_SSA/V_REFL are a straight-line linear conversion. All other input voltages will result
in $FF if greater than V_REFH and $00 if less than V_SSA/V_REFL.
Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The ADC
starts a conversion on the first rising edge of the ADC internal clock immediately
following a write to the ADSCR. If the ADC internal clock is selected to run at
1 MHz, then one conversion will take 16 µs to complete. But since the ADC can run
almost completely asynchronously to the bus clock, (for example, the ADC is
configured to derive its internal clock from CGMXCLK and the bus clock is being
derived from the PLL within the CGM [CGMOUT]), this 16-µs conversion can take
up to 17 µs to complete. This worst-case could occur if the write to the ADSCR
happened directly after the rising edge of the ADC internal clock causing the
conversion to wait until the next rising edge of the ADC internal clock. With a 1-MHz
ADC internal clock, the maximum sample rate is 59 kHz to 62 kHz. Refer to 17.6
ADC Characteristics
Conversion Time = ¹⁶^to¹ï£§⁷ ^AD^C^C^lo^ck^C^yc^les
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
3.3.4 Continuous Conversion Mode
In the continuous conversion mode, the ADC continuously converts the selected
channel, filling the ADC data register with new data after each conversion. Data
from the previous conversion will be overwritten whether that data has been read
or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADC
status control register, $0038) is set after each conversion and can be cleared by
writing the ADC status and control register or reading of the ADC data register.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See 17.6 ADC
Characteristics for accuracy information.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt
after each ADC conversion. A CPU interrupt is generated if the COCO bit is at
Data Sheet
48
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor