MC68HC08AS32 Datasheet, PDF (162/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

A good time to toggle the TE bit is when the SCTE bit becomes set and just before
writing the next byte to the SCDR.
12.3.7 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the
polarity of transmitted data. All transmitted values, including idle, break, start,
and stop bits, are inverted when TXINV is at logic 1. (See 12.8.1 SCI Control
Register 1.)
12.3.8 Transmitter Interrupts
The following conditions can generate CPU interrupt requests from the SCI
transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the
SCDR has transferred a character to the transmit shift register. SCTE can
generate a transmitter CPU interrupt request. Setting the SCI transmit
interrupt enable bit, SCTIE (SCC2), enables the SCTE bit to generate
transmitter CPU interrupt requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that the
transmit shift register and the SCDR are empty and that no break or idle
character has been generated. The transmission complete interrupt enable
bit, TCIE (SCC2), enables the TC bit to generate transmitter CPU interrupt
requests.
12.3.9 Receiver
Figure 12-6 shows the structure of the SCI receiver.
12.3.10 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in
SCI control register 1 (SCC1) determines character length. When receiving 9-bit
data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving
8-bit data, bit R8 is a copy of the eighth bit (bit 7).
12.3.11 Character Reception
During an SCI reception, the receive shift register shifts characters in from the
PTE1/RxD pin. The SCI data register (SCDR) is the read-only buffer between the
internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of
the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status
register 1 (SCS1) becomes set, indicating that the received byte can be read. If the
SCI receive interrupt enable bit, SCRIE (SCC2), is also set, the SCRF bit
generates a receiver CPU interrupt request.
Data Sheet
162
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor