MC68HC08AS32 Datasheet, PDF (168/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

12.4.1 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive shift register
shifted in a new character before the previous character was read from the
SCDR. The previous character remains in the SCDR, and the new character
is lost. The overrun interrupt enable bit, ORIE (SCC3), enables OR to
generate SCI error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming
data or break characters, including start, data, and stop bits. The noise error
interrupt enable bit, NEIE (SCC3), enables NF to generate SCI error CPU
interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where
the receiver expects a stop bit. The framing error interrupt enable bit, FEIE
(SCC3), enables FE to generate SCI error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity
error in incoming data. The parity error interrupt enable bit, PEIE (SCC3),
enables PE to generate SCI error CPU interrupt requests.
12.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
12.5.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait
mode, the SCI module registers are not accessible by the CPU. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT instruction.
12.5.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP
instruction does not affect SCI register states. SCI module operation resumes after
an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during
an SCI transmission or reception results in invalid data.
12.6 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules
can be cleared during interrupts generated by the break module. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear status bits
during the break state.
Data Sheet
168
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor