MC68HC08AS32 Datasheet, PDF (147/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
NOTE:
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TCLK–PTD0/ATD8 are seven of the 15 analog-to-digital
converter channels. The ADC channel select bits, CH[4:0], determine whether
the PTD6/ATD14/TCLK–PTD0/ATD8 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of this
corresponding bit in the port B data register occurs, the data will be 0 if the data
direction for this bit is programmed as an input. Otherwise, the data will reflect
the value in the data latch. (See Section 3. Analog-to-Digital Converter
(ADC).)
Data direction register D (DDRD) does not affect the data direction of port D pins
that are being used by the ADC. However, the DDRD bits always determine
whether reading port D returns the states of the latches or logic 0.
TCLK — Timer Clock Input Bit
The PTD6/ATD14/TCLK pin is the external clock input for the TIM. The
prescaler select bits, PS[2:0], select PTD6/ATD14/TCLK as the TIM clock input.
(See 15.8.1 TIM Status and Control Register.) When not selected as the TIM
clock, PTD6/ATD14/TCLK is available for general-purpose I/O or as an ADC
channel.
Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin as the
clock input for the TIM.
11.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an
output. Writing a logic 1 to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
0
0
0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Figure 11-12. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
NOTE:
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[6:0],
configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Avoid glitches on port D pins by writing to the port D data register before changing
data direction register D bits from 0 to 1.
Figure 11-13 shows the port D I/O logic.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
147