MC68HC08AS32 Datasheet, PDF (189/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 13-7. Sources of Internal Reset
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other
chips within a system built around the MCU.
13.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR)
generates a pulse to indicate that power-on has occurred. The external reset pin
(RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles.
Another 64 CGMXCLK cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits
in the register are cleared.
See Figure 13-8.
13.3.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the COP bit in
the SIM reset status register (SRSR) if the COPD bit in the MOR register is at
logic 0. (See Section 6. Computer Operating Properly (COP).)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
189