MC68HC08AS32 Datasheet, PDF (206/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

The SPR1 and SPR0 bits control the baud rate generator and determine the speed
of the shift register. (See 14.13.2 SPI Status and Control Register.) Through the
SPSCK pin, the baud rate generator of the master also controls the shift register of
the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the
slave on the master’s MISO pin. The transmission ends when the receiver full bit,
SPRF (SPSCR), becomes set. At the same time that SPRF becomes set, the byte
from the slave transfers to the receive data register. In normal operation, SPRF
signals the end of a transmission. Software clears SPRF by reading the SPI status
and control register and then reading the SPI data register. Writing to the SPI data
register clears the SPTE bit.
14.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit (SPCR $0010) is clear. In
slave mode the SPSCK pin is the input for the serial clock from the master MCU.
Before a data transmission occurs, the SS pin of the slave MCU must be at logic 0.
SS must remain low until the transmission is complete. (See 14.6.2 Mode Fault
Error.)
In a slave SPI module, data enters the shift register under the control of the serial
clock from the master SPI module. After a byte enters the shift register of a slave
SPI, it is transferred to the receive data register, and the SPRF bit (SPSCR) is set.
To prevent an overflow condition, slave software then must read the SPI data
register before another byte enters the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus
clock speed, which is twice as fast as the fastest master SPSCK clock that can be
generated. The frequency of the SPSCK for an SPI configured as a slave does not
have to correspond to any SPI baud rate. The baud rate only controls the speed of
the SPSCK generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency less than or
equal to the bus speed.
When the master SPI starts a transmission, the data in the slave shift register
begins shifting out on the MISO pin. The slave can load its shift register with a new
byte for the next transmission by writing to its transmit data register. The slave must
write to its transmit data register at least one bus cycle before the master starts the
next transmission. Otherwise, the byte already in the slave shift register shifts out
on the MISO pin. Data written to the slave shift register during a a transmission
remains in a buffer until the end of the transmission.
Data Sheet
206
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor