MC68HC08AS32 Datasheet, PDF (109/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Data Sheet — MC68HC08AS32
Section 6. Computer Operating Properly (COP)
6.1 Introduction
This section describes the computer operating properly (COP) module, a
free-running counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by periodically
clearing the COP counter.
6.2 Functional Description
Figure 6-1 shows the structure of the COP module.
The COP counter is a free-running 6-bit counter preceded by the 12-bit system
integration module (SIM) counter. COP timeouts are determined strictly by the
CGM crystal oscillator clock signal (CGMXCLK), not the CGMOUT signal (see
Figure 5-1. CGM Block Diagram).
If not cleared by software, the COP counter overflows and generates an
asynchronous reset after (2¹³ – 2⁴) or (2¹⁸ – 2⁴) CGMXCLK cycles, depending
upon COPS bit in the MOR register ($001F) (See Section 10. Mask Options.)
With a 4.9152-MHz crystal and the COPS bit in the MOR register ($001F) set to a
logic 1, the COP timeout period is approximately 53.3 ms. Writing any value to
location $FFFF before overflow occurs clears the COP counter, clears bits 12
through 4 of the SIM counter, and prevents reset. A CPU interrupt routine can be
used to clear the COP.
NOTE:
The COP should be serviced as soon as possible out of reset and before entering
or after exiting stop mode to guarantee the maximum selected amount of time
before the first timeout.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit
in the SIM reset status register (SRSR) (see 13.7.2 SIM Reset Status Register).
While the microcontroller is in monitor mode, the COP module is disabled if the
RST pin or the IRQ pin is held at V_DD + V_HI (see 17.4 5.0-Volt DC Electrical
Characteristics). During a break state, V_DD + V_HI on the RST pin disables the
COP module.
NOTE:
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from generating a
reset even while the main program is not working properly. The one exception to
this is wait mode (see 6.7.1 Wait Mode).
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
109