MC68HC08AS32 Datasheet, PDF (233/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Reset does not affect the contents of the input capture channel (TCHxH–TCHxL)
registers.
15.3.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a
programmable polarity, duration, and frequency. When the counter reaches the
value in the registers of an output compare channel, the TIM can set, clear, or
toggle the channel pin. Output compares can generate TIM CPU interrupt
requests.
15.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as
described in 15.3.3 Output Compare. The pulses are unbuffered because
changing the output compare value requires writing the new value over the old
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare
value could cause incorrect operation for up to two counter overflow periods. For
example, writing a new value before the counter reaches the old value but after the
counter reaches the new value prevents any compare during that counter overflow
period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new
value before it is written.
Use the following methods to synchronize unbuffered changes in the output
compare value on channel x:
• When changing to a smaller value, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current output
compare pulse. The interrupt routine has until the end of the counter
overflow period to write the new value.
• When changing to a larger output compare value, enable
TIM overflow interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current counter
overflow period. Writing a larger value in an output compare interrupt routine
(at the end of the current pulse) could cause two output compares to occur
in the same counter overflow period.
15.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose
output appears on the PTE2/TCH0 pin. The TIM channel registers of the linked pair
alternately control the output.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
233