MC68HC08AS32 Datasheet, PDF (102/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

5.5.3 PLL Programming Register
The PLL programming register contains the programming information for the
modulo feedback divider and the programming information for the hardware
configuration of the VCO.
Address:
Read:
Write:
Reset:
$001E
Bit 7
6
5
4
3
2
1
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
0
1
1
0
0
1
1
Figure 5-6. PLL Programming Register (PPG)
Bit 0
VRS4
0
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 5.3.2 Phase-Locked Loop Circuit (PLL).) A value
of $0 in the multiplier select bits configures the modulo feedback divider the
same as a value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Table 5-1. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
NOTE:
The multiplier select bits have built-in protection that prevents them from being
written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier, L,
which controls the hardware center-of-range frequency, f_VRS, (see 5.3.2
Phase-Locked Loop Circuit (PLL)). VRS[7:4] cannot be written when the
PLLON bit in the PLL control register (PCTL) is set. (See 5.3.2.5 Special
Programming Exceptions.) A value of $0 in the VCO range selects bits,
disables the PLL, and clears the BCS bit in the PCTL. (See 5.3.3 Base Clock
Data Sheet
102
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor