MC68HC08AS32 Datasheet, PDF (138/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode.(See Section 9. Low-Voltage
Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
ROMSEC — ROM Security Bit
ROMSEC enables the ROM security feature. Setting the ROMSEC bit prevents
reading of the ROM contents. Access to the ROM is denied to unauthorized
users of customer-specified software.
1 = ROM security enabled
0 = ROM security disabled
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See Section 9.
Low-Voltage Inhibit (LVI).)
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. (See Section 9. Low-Voltage Inhibit (LVI).)
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles
instead of a 4096-CGMXCLK cycle delay. (See 15.5.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Timeout Bit
COPS selects the short COP timeout period. (See Section 6. Computer
Operating Properly (COP).)
1 = COP timeout period is 2¹³â€“2⁴ CGMXCLK cycles.
0 = COP timeout period is 2¹⁸–2⁴ CGMXCLK cycles.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 6. Computer Operating
Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Data Sheet
138
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor