MC68HC08AS32 Datasheet, PDF (75/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

CRC Error
A cyclical redundancy check (CRC) error is detected when the data bytes and
CRC byte of a received message are processed and the CRC calculation result
is not equal to $C4. The CRC code will detect any single and 2-bit errors, as well
as all 8-bit burst errors and almost all other types of errors. The CRC error flag
($18 in BSVR) is set when a CRC error is detected. (See 4.6.4 BDLC State
Vector Register.)
Symbol Error
A symbol error is detected when an abnormal (invalid) symbol is detected in a
message being received from the J1850 bus. However, if the BDLC is
transmitting when this happens, it will be treated as a loss of arbitration ($14 in
BSVR) rather than a transmitter error. The ($1C) symbol invalid or the
out-of-range flag is set when a symbol error is detected. Therefore, ($1C)
symbol invalid flag is stacked behind the ($14) LOA flag during a transmission
error process. (See 4.6.4 BDLC State Vector Register.)
Framing Error
A framing error is detected if an EOD or EOF symbol is detected on a non-byte
boundary from the J1850 bus. A framing error also is detected if the BDLC is
transmitting the EOD and instead receives an active symbol. The ($1C) symbol
invalid or the out-of-range flag is set when a framing error is detected. (See 4.6.4
BDLC State Vector Register.)
Bus Fault
If a bus fault occurs, the response of the BDLC will depend upon the type of bus
fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to a passive
state before it will attempt to transmit a message. As long as the short remains,
the BDLC will never attempt to transmit a message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit
the message, and then detect a transmission error ($1C in BSVR), since the
short to ground would not allow the bus to be driven to the active (dominant)
SOF state. The BDLC will abort that transmission and wait for the next CPU
command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the
BDLC will resume normal operation. If the bus fault is permanent, it may result
in permanent loss of communication on the J1850 bus. (See 4.6.4 BDLC State
Vector Register.)
BREAK — Break
If a BREAK symbol is received while the BDLC is transmitting or receiving, an
invalid symbol ($1C in BSVR) interrupt will be generated. Reading the BSVR
register (see 4.6.4 BDLC State Vector Register) will clear this interrupt
condition. The BDLC will wait for the bus to idle, then wait for a start-of-frame
(SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It can only receive a BREAK
symbol from the J1850 bus.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
75