MC68HC08AS32 Datasheet, PDF (133/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Data Sheet — MC68HC08AS32
Section 9. Low-Voltage Inhibit (LVI)
9.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the
voltage on the V_DD pin and can force a reset when the V_DD voltage falls to the LVI
trip voltage.
9.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of V_DD pin level
9.3 Functional Description
Figure 9-1 shows the structure of the LVI module. The LVI is enabled out of reset.
The LVI module contains a bandgap reference circuit and comparator. The LVI
power bit, LVIPWR, enables the LVI to monitor V_DD voltage. The LVI reset bit,
LVIRST, enables the LVI module to generate a reset when V_DD falls below a
voltage, V_LVIF, and remains at or below that level for nine or more consecutive CPU
cycles. LVISTOP, enables the LVI module during stop mode. This will ensure when
the STOP instruction is implemented, the LVI will continue to monitor the voltage
level on V_DD. LVIPWR, LVISTOP, and LVIRST are in the MOR register ($001F)
(see Section 10. Mask Options). Once an LVI reset occurs, the MCU remains in
reset until V_DD rises above a voltage, V_LVIR. The output of the comparator controls
the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to
external peripheral devices.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
133