MC68HC08AS32 Datasheet, PDF (141/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

11.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an
output. Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
0
0
0
Figure 11-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
NOTE:
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0],
configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
Avoid glitches on port A pins by writing to the port A data register before changing
data direction register A bits from 0 to 1.
Figure 11-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAx
READ PTA ($0000)
Figure 11-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch.
When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the
pin. The data latch can always be written, regardless of the state of its data
direction bit. Table 11-1 summarizes the operation of the port A pins.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
141