MC68HC08AS32 Datasheet, PDF (79/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

CLKS — Clock Bit
The nominal BDLC operating frequency (f_BDLC) must always be 1.048576 MHz
or 1 MHz for J1850 bus communications to take place. The CLKS register bit
allows the user to select the frequency (1.048576 MHz or 1 MHz) used to adjust
symbol timing automatically.
1 = Binary frequency (1.048576 MHz) selected for f_BDLC
0 = Integer frequency (1 MHz) selected for f_BDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (f_BDLC) which
defines the basic timing resolution of the MUX interface. They may be written
only once after reset, after which they become read-only bits.
The nominal frequency of f_BDLC must always be 1.048576 MHz or 1.0 MHz
for J1850 bus communications to take place. Hence, the value programmed
into these bits is dependent on the chosen MCU system clock frequency per
Table 4-3.
Table 4-3. BDLC Rate Selection
f_XCLK Frequency
R1
1.049 MHz
0
2.097 MHz
0
4.194 MHz
1
8.389 MHz
1
1.000 MHz
0
2.000 MHz
0
4.000 MHz
1
8.000 MHz
1
R0
Division
f_BDLC
0
1
1.049 MHz
1
2
1.049 MHz
0
4
1.049 MHz
1
8
1.049 MHz
0
1
1.00 MHz
1
2
1.00 MHz
0
4
1.00 MHz
1
8
1.00 MHz
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt requests in
run mode. It does not affect CPU interrupt requests when exiting the BDLC stop
or BDLC wait modes. Interrupt requests will be maintained until all of the
interrupt request sources are cleared by performing the specified actions upon
the BDLC’s registers. Interrupts that were pending at the time that this bit is
cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the BDLC, the
BDLC state vector register (BSVR) can be polled periodically by the
programmer to determine BDLC states. See 4.6.4 BDLC State Vector
Register for a description of the BSVR.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
79