MC68HC08AS32 Datasheet, PDF (208/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

reconfigured as general-purpose I/O not affecting the SPI. (See 14.6.2 Mode Fault
Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe.
Therefore, the slave must begin driving its data before the first SPSCK edge, and
a falling edge on the SS pin is used to start the transmission. The SS pin must
be toggled high and then low again between each byte transmitted as shown in
Figure 14-6.
SCK CYCLE #
FOR REFERENCE
SCK CPOL = 0
1
2
3
4
5
6
7
8
SCK CPOL = 1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS TO SLAVE
CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 14-5. Transmission Format (CPHA = 0)
MISO/MOSI
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 14-6. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the
transmission. This causes the SPI to leave its idle state and begin driving the MISO
pin with the MSB of its data. Once the transmission begins, no new data is allowed
into the shift register from the transmit data register. Therefore, the SPI data
register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
Data Sheet
208
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor