MC68HC08AS32 Datasheet, PDF (214/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
NOTE:
NOTE:
To prevent bus contention with another master SPI after a mode fault error, clear
all data direction register (DDR) bits associated with the SPI shared port pins.
Setting the MODF flag (SPSCR) does not clear the SPMSTR bit. Reading
SPMSTR when MODF = 1 will indicate that a MODE fault error occurred in either
master mode or slave mode.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high
during a transmission. When CPHA = 0, a transmission begins when SS goes low
and ends once the incoming SPSCK returns to its idle level after the shift of the
eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves
its idle level and SS is already low. The transmission continues until the SPSCK
returns to its IDLE level after the shift of the last data bit. (See 14.5 Transmission
Formats.)
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later
unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens
because SS at logic 0 indicates the start of the transmission (MISO driven out with
the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and
then later unselected with no transmission occurring. Therefore, MODF does not
occur since a transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU
interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit
or reset the SPI in any way. Software can abort the SPI transmission by toggling
the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if a
transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR register. This
entire clearing procedure must occur with no MODF condition existing or else the
flag will not be cleared.
14.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests, as
shown in Table 14-3.
Flag
SPTE (transmitter empty)
SPRF (receiver full)
OVRF (overflow)
MODF (mode fault)
Table 14-3. SPI Interrupts
Request
SPI transmitter CPU Interrupt request (SPTIE = 1)
SPI receiver CPU interrupt request (SPRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1, MODFEN = 1)
Data Sheet
214
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor