MC68HC08AS32 Datasheet, PDF (196/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Wait mode also can be exited by a reset or break. A break interrupt during wait
mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register
(SBSR). If the COP disable bit, COPD, in the mask option register (MOR $001F) is
logic 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-13. Wait Mode Entry Timing
Figure 13-14 and Figure 13-15 show the timing for wait recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 13-14. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 13-15. Wait Recovery from Internal Reset
Data Sheet
196
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor