MC68HC08AS32 Datasheet, PDF (77/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

4.6.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of different
external transceivers. The default delay value is16 µs. Timing adjustments from
9 µs to 24 µs in steps of 1 µs are available. The BARD register can be written only
once after each reset, after which they become read-only bits. The register may be
read at any time.
Address: $003B
Bit 7
6
5
Read: _ATE
RXPOL
0
Write:
R
Reset:
1
1
0
R = Reserved
4
3
2
1
Bit 0
0
BO3
BO2
BO1
BO0
R
0
0
1
1
1
Figure 4-17. BDLC Analog and Roundtrip Delay Register (BARD)
NOTE:
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the on-board or
an off-chip analog transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming
signal on the receive pin. Some external analog transceivers invert the receive
signal from the J1850 bus before feeding it back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the J1850 bus;
for example, the external transceiver does not invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts the receive
signal from the J1850 bus
B03–B00 — BARD Offset Bits
Table 4-2 shows the expected transceiver delay with respect to BARD offset
values.
Table 4-2. BDLC Transceiver Delay
BARD Offset Bits B0[3:0]
0000
0001
0010
0011
0100
Corresponding Expected
Transceiver’s Delays (µs)
9
10
11
12
13
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
77