MC68HC08AS32 Datasheet, PDF (186/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Table 13-1 shows the internal signal names used in this section.
Table 13-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
13.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals
on the MCU. The system clocks are generated from an incoming clock, CGMOUT,
as shown in Figure 13-4. This clock can come from either an external oscillator or
from the on-chip PLL. (See Section 5. Clock Generator Module (CGM).)
13.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output
(CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. (See
Section 5. Clock Generator Module (CGM).)
13.2.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI) module
generates a reset, the clocks to the CPU and peripherals are inactive and held in
an inactive phase until after 4096 CGMXCLK cycles. The RST pin is driven low by
the SIM during this entire period. The bus clocks start upon completion of the
timeout.
Data Sheet
186
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor