MC68HC08AS32 Datasheet, PDF (251/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Data Sheet — MC68HC08AS32
Section 16. Development Support
16.1 Introduction
This section describes the break module, the monitor read-only memory (MON),
and the monitor mode entry methods.
16.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow
at a defined address to enter a background program.
Features of the break module include:
• Accessible I/O registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
16.2.1 Functional Description
When the internal address bus matches the value written in the break address
registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM
then causes the CPU to load the instruction register with a software interrupt
instruction (SWI) after completion of the current CPU instruction. The program
counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches
the contents of the break address registers
• Software writes a logic 1 to the BRKA bit in the break status and control
register.
When a CPU-generated address matches the contents of the break address
registers, the break interrupt begins after the CPU completes its current instruction.
A return-from-interrupt instruction (RTI) in the break routine ends the break
interrupt and returns the MCU to normal operation. Figure 16-1 shows the
structure of the break module.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
251