MC68HC08AS32 Datasheet, PDF (164/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Addr.
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Register Name
SCI Control Register 1
(SCC1)
See page 170.
SCI Control Register 2
(SCC2)
See page 172.
SCI Control Register 3
(SCC3)
See page 174.
SCI Status Register 1
(SCS1)
See page 175.
SCI Status Register 2
(SCS2)
See page 178.
SCI Data Register
(SCDR)
See page 179.
SCI Baud Rate Register
(SCBR)
See page 179.
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
LOOPS
0
SCTIE
0
R8
R
U
SCTE
R
1
0
R
0
R7
T7
0
R
0
R
6
ENSCI
0
TCIE
0
T8
U
TC
R
1
0
R
0
R6
T6
5
TXINV
0
SCRIE
0
R
0
SCRF
R
0
0
R
0
R5
T5
0
R
SCP1
0
0
= Reserved
4
3
M
WAKE
0
0
ILIE
TE
0
0
R
ORIE
0
0
IDLE
OR
R
R
0
0
0
0
R
R
0
0
R4
R3
T4
T3
Unaffected by reset
SCP0
R
0
0
Table 12-1. SCI Receiver I/O Register Summary
2
ILTY
0
RE
0
NEIE
0
NF
R
0
0
R
0
R2
T2
SCR2
0
1
PEN
0
RWU
0
FEIE
0
FE
R
0
BKF
R
0
R1
T1
SCR1
0
Bit 0
PTY
0
SBK
0
PEIE
0
PE
R
0
RPF
R
0
R0
T0
SCR0
0
12.3.12 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an
internal signal with a frequency 16 times the baud rate. To adjust for baud rate
mismatch, the RT clock is resynchronized at the following times (see Figure 12-7):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the
majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1
and the majority of the next RT8, RT9, and RT10 samples returns a valid
logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a
logic 0 preceded by three logic 1s. When the falling edge of a possible start bit
occurs, the RT clock begins to count to 16.
Data Sheet
164
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor