MC68HC08AS32 Datasheet, PDF (136/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

9.6.2 Stop Mode
NOTE:
With the LVISTOP and LVIPWR bits in the configuration register programmed to a
logic 1, the LVI module will be active after a STOP instruction. Because CPU clocks
are disabled during stop mode, the LVI trip must bypass the digital filter to generate
a reset and bring the MCU out of stop.
With the LVIPWR bit in the MOR register programmed to logic 1 and the LVISTOP
bit at a logic 0, the LVI module will be inactive after a STOP instruction.
If the LVIPWR bit is at logic 1, the LVISTOP bit must be at logic 0 to meet the
minimum stop mode I_DD specification.
Data Sheet
136
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor